Senior Ph.D. student in Computer Engineering at the University of Central Florida, working at the seam between computer architecture and AI/ML systems. I design hardware-software co-optimized accelerators for GNNs, DNNs, and sparse workloads — translating model-level insight into dataflow, tiling, and silicon-aware decisions. Published at NeurIPS, and MICRO. I like the parts of the stack where the abstraction starts to leak.
A mix of accelerator-design research, GPU-systems work, and embedded builds. Drop me a line if any of them sparks something.
Gated multi-hop message passing rooted in an information-theoretic objective that maximizes relevant signal across hops. SOTA accuracy on 16 heterophilic benchmarks, 12× lower GPU memory, and 20× inference speedup via weight sharing and fixed-dim design.
Reformulated SpMM as a graph-transformation problem: non-contiguous tiling, custom PE µ-architecture, and a Bidirectional Fiber Tree compression format. Cycle-accurate simulation (Ramulator + HBM): 3.2× lower off-chip traffic, 4.8× better energy efficiency, 4.3× average speedup over Sextans.
Adaptive post-training quantization with mixed-precision allocation for Capsule Networks, driven by layer-wise vulnerability analysis. Power-of-Two scalers replace floating-point ops with hardware bitshifts — 8.67× weight compression, 4.56× activation reduction, 4× speedup, within 1% of full-precision accuracy.
Fault-injection study tracing how Single-Event Upsets propagate through dynamic-routing layers, with mitigation strategies for soft-error tolerance — feeding directly into the layer-wise vulnerability ranking used in the quantization work.
Embedded firmware in C/C++ for ARM-based microcontrollers, paired with OpenCV-based ball-detection pipelines on the host side. End-to-end build of the perception, control, and wireless command loop.
A complete MIPS ISA datapath built from gate-level primitives — fetch, decode, ALU, hazard handling, and memory — simulated and verified inside Proteus. Same material I later TA'd for UCF's Computer Organization course.
Course project benchmarking parallel primitives across CPU thread pools and CUDA kernels — communication, contention, warp coordination, and the gap between Amdahl and reality.
A condensed log of papers — full list and citations on Google Scholar.
A reverse-chronological dump of where I've been and what I worked on.
Information-theoretic gated message passing — SOTA accuracy on 16 heterophilic benchmarks, 12× lower GPU memory, 20× inference speedup. NeurIPS '25 (GAMMA).
Graph-transformation framework, custom PE µ-arch, and a Bidirectional Fiber Tree compression format. 3.2× off-chip reduction, 4.8× energy gains, 4.3× speedup vs. Sextans. MICRO '25.
Delivered lectures on the MIPS ISA and processor hardware design — datapath, control, hazards — with concept-driven exercises to build student debugging intuition.
Designed Arbiter PUFs in 32 nm and 14 nm CNTFET libraries with multi-valued logic, simulated in HSPICE. 99.56% (ternary) and 99.15% (quaternary) reliability across temperature and supply variations, deviation under 2%.
Adaptive post-training quantization with layer-wise vulnerability analysis and Power-of-Two scalers (bitshift-friendly). 8.67× weight compression, 4.56× activation reduction, accuracy within 1% of FP baseline.
Embedded software in C/C++ for ARM microcontrollers; OpenCV-based ball-detection pipelines on the host side. End-to-end perception, control, and wireless command loop.
University of Central Florida — Orlando, FL. Research: efficient AI systems, hardware accelerators, and GPU kernels for sparse and irregular workloads.
Shiraz University — Shiraz, Iran. Ranked 1st in M.Sc. studies. Thesis on capsule-network reliability under single-event upsets and quantization.
Shahid Bahonar University — Kerman, Iran. Foundation in digital design, architecture, and embedded systems.
Reviewer — NeurIPS, ICML, MLSys, IEEE TC
Things I reach for daily. Bold = primary, the rest are supporting cast.
Happy to talk research, AI accelerators, GPU systems — or just nerdy side projects.